标签：RISC-V

4 篇文章

2026年7月1日

CH569/CH565 Deep Dive: RISC-V Core + USB 3.0 SuperSpeed — The Complete Guide to China's High-Speed Interface MCU

WCH's CH569/CH565 is the world's first RISC-V MCU with a built-in USB 3.0 PHY, integrating Gigabit Ethernet, SerDes fiber-optic direct drive, HSPI high-speed parallel interface (3.8Gbps), EMMC, and hardware encryption/decryption. This article provides an in-depth analysis of the chip architecture, development environment, peripheral usage, and typical application scenarios.

2026年7月1日

CH569/CH565 深度解析：RISC-V 内核 + USB 3.0 SuperSpeed 国产高速接口 MCU 完全指南

沁恒 CH569/CH565 是全球首款内置 USB 3.0 PHY 的 RISC-V MCU，集成千兆以太网、SerDes 光纤直驱、HSPI 高速并口（3.8Gbps）、EMMC、硬件加解密。本文深度解析芯片架构、开发环境、外设实战与典型应用场景。

2026年5月21日

RISC-V 架构入门：从原理到第一块开发板

写在前面 过去二十年，处理器架构市场基本被两家瓜分：Intel 的 x86 统治 PC 和服务，ARM 统治移动端和 IoT。你想自己做一颗芯片？抱歉，先交一笔不便宜的授权费。 RISC-V 的出现打破了这个局面。 RISC-V 是一个完全开源的指令集架构（ISA）。任何人可以免费使用它设计、制造、销售芯片或基于 RISC-V 的产品，而无需向任何公司支付许可费。它由加州大学伯克利分校的...

2026年5月21日

RISC-V Architecture Getting Started: From Principles to Your First Dev Board

Over the past two decades, the processor architecture market has been dominated by two players: Intel's x86 rules PCs and servers, while ARM dominates mobile and IoT. Want to design your own chip? Sorry — pay a hefty licensing fee first. RISC-V changed the game. RISC-V is a completely open-source instruction set architecture (ISA). Anyone can freely use it to design, manufacture, and sell chips or RISC-V-based products without paying licensing fees to any company. Initiated by Professor Krste Asanović and his team at UC Berkeley in 2010, it has become the hottest new force in the chip industry.

暂无内容