Aug 9, 2026 Embedded Development

PCB Design Complete Guide: From KiCad Beginner to Four-Layer Board Signal Integrity Practice

From a simple ESP32 breakout board to a four-layer high-speed PCB, the only difference is a complete methodology. Many people fail on their first prototype run—signal distortion, EMI exceeding limits, power supply ripple out of control—the problem is often not the components, but the board design itself.

This article breaks down PCB design into a complete pipeline: KiCad schematic → footprint assignment → layout and routing → four-layer board stackup design → impedance and crosstalk control → power integrity → DRC and Gerber output → prototyping troubleshooting, explained all at once.

1. Why Choose KiCad as the Main Tool?

Altium Designer and Eagle are either expensive or limited. KiCad’s advantages are straightforward:

Completely free and open source, no feature restrictions, can be used for commercial projects
Cross-platform, works on Windows / macOS / Linux
Active community, with growing plugins and component libraries
Professional capabilities, supports multi-layer boards, differential pairs, impedance control

Many startup teams’ products started with KiCad. No need to wait until “there’s budget” to learn PCB design.

Installation and Library Preparation

# Ubuntu / Debian
sudo apt update && sudo apt install kicad

# macOS (Homebrew)
brew install --cask kicad

# Windows: Download installer from https://www.kicad.org/download/

After installation, the first thing to do is confirm the official libraries are loaded:

Preferences → Manage Symbol Libraries   → Confirm "kicad:symbols" is connected
Preferences → Manage Footprint Libraries → Confirm "kicad:footprints" is connected

KiCad 8’s built-in official libraries already cover the vast majority of common components, no additional downloads needed.

2. Schematic Drawing: Get It Right to Build It Right

After creating a new project, enter Eeschema (schematic editor). First set File → Page Settings (A4 or A3), fill in project name and author to make exported PDFs more professional.

Two Common Ways to Place Core Components

Press A to open the component library browser, search by keyword (e.g., ESP32, AMS1117), double-click to place on the schematic.
Copy and reuse modules from existing hierarchical subsheets (power supply, decoupling, LED indicators, etc.) to maintain consistent style.

Four Core Tips for Schematic Drawing

Shortcuts first: A add component, W wire, M move, R rotate, L net label, P power flag. Once proficient, it’s three times faster than using the mouse.
Labels instead of wires: For cross-region signals with the same name (GND, 3V3), use net labels (L) instead of physical wires to keep the schematic cleaner.
Hierarchical design: When circuits are complex, use Add Hierarchical Sheet to split power supply, main controller, and interfaces into subsheets for easier management and reuse.
Always run ERC: After drawing, run Tools → Electrical Rules Checker to catch low-level errors like floating power pins, undriven nets, etc.

Power Tree Design

A clear power tree greatly improves schematic readability:

USB 5V ──→ AMS1117-3.3 ──→ 3.3V net
                              ├── ESP32 3V3
                              ├── Decoupling capacitors 100nF × 3
                              └── LED indicator circuit

Use P key to label +5V, +3.3V, GND, power flags are globally connected. Note that ESP32 can consume up to 500mA during Wi-Fi transmission. The AMS1117 heat sink pad should have plenty of copper pour on the PCB, and add a 10μF filter capacitor at the input to prevent voltage drop causing restarts.

3. Assigning Footprints

Press Ctrl+F8 to open the Footprint Assigner. Footprints determine the physical size of components on the PCB:

Component	Recommended Footprint	Notes
ESP32-WROOM-32	`Module:ESP32-WROOM-32`	Official module footprint
AMS1117-3.3	`Package_TO_SOT_SMD:SOT-223`	Standard SOT-223
Resistor 0805	`Resistor_SMD:R_0805_2012Metric`	Common SMD size
Capacitor 0805	`Capacitor_SMD:C_0805_2012Metric`	Same size as resistor
USB Type-C	`Connector_USB:USB_C_Receptacle_..._16pin`	Confirm pin spacing
LED	`LED_SMD:LED_0805_2012Metric`	SMD LED

Experience: 0805 is most beginner-friendly, can be hand-soldered; don’t challenge 0402 right away unless you plan to use reflow soldering.

4. PCB Layout and Routing: From Blank Board to Complete Traces

Press F8 to jump from schematic to Pcbnew, first Tools → Update Footprints from Schematic to sync.

Five Layout Principles

Group by function: Power supply, main controller, interfaces, analog signals each in their own block to avoid mutual interference.
Place critical components first: Connectors, large chips, heat dissipation components’ positions determine overall routing quality.
Decoupling capacitors close to pins: The farther away, the worse the high-frequency decoupling effect.
Reserve space for heat dissipation and mechanics: Mounting holes, heat sink pads, enclosure interference all need to be considered in advance.
Clear signal flow: Input → processing → output in one direction, avoid routing going back and crossing.

Draw the board outline on the Edge.Cuts layer (rectangle or import DXF). For ESP32 breakout boards, 50×30mm is recommended, with a 3mm mounting hole at each corner, and cross marks on the F.SilkS layer.

Routing Rule Settings

In Design Rules → Classes, set at least three categories:

Net Class	Trace Width	Via Size	Purpose
Power	0.5mm (20mil)	0.8/1.6mm	Power and ground
Signal	0.25mm (10mil)	0.4/0.8mm	Normal signals
Diff Pair	0.2mm (8mil)	0.3/0.8mm	Differential signals

Core Routing Points

Ground first: Lay down thick ground net traces first, then route signals. Ground is the reference for all signals.
Avoid 90° corners: Keep KiCad’s default 45°. At high frequencies, 90° introduces impedance discontinuity.
Thicken power traces: At least 0.5mm, 1mm+ for high current; ESP32 power traces recommended ≥ 0.6mm.
Equal length for high-speed signals: Length difference for SPI and other differential or parallel buses controlled within 5mm.
Minimize vias: Each via adds about 0.1Ω impedance and parasitic inductance. Don’t use them unless necessary.
Orthogonal routing between layers: Signal traces on adjacent layers should run perpendicular to reduce inter-layer coupling.

Four Key Points for ESP32 Breakout Board Routing

Keep traces between crystal and ESP32 as short as possible, with ground guard.
Keep antenna area clear, no traces or copper pour allowed in the onboard antenna area.
In GPIO-dense areas, prioritize using vias to change layers, avoid long-distance serpentine routing.
Reserve test points for critical signals like BOOT, EN for easy debugging.

Four-Step Copper Pour Method

Press B to add copper pour areas on both F.Cu and B.Cu.
In copper pour properties, set Net to GND, and check “Keep out of zones” to avoid encroaching on signals.
Place a ground via every 2~3cm to connect the two copper layers, reducing ground impedance.
Set Clearance to 0.2mm, pour copper around high-frequency signal traces and connect to ground to form guard traces.

Benefits of copper pour: low-impedance ground plane, helps with heat dissipation, shields EMI, improves PCB mechanical strength. For fill mode, choose Hatch (grid) to reduce thermal stress, suitable for hand soldering; choose Solid for better conductivity.

5. Four-Layer Board Stackup Design: Foundation of Signal Integrity

Upgrading from a two-layer board to a four-layer board, the core benefit is two complete reference planes. But the prerequisite is a reasonable stackup scheme.

Scheme A (Recommended): Signal-Ground-Power-Signal

Layer	Name	Purpose
L1	Top (signal layer)	High-speed signals, critical signals
L2	GND (ground plane)	Complete reference plane, return path for all high-speed signals
L3	PWR (power plane)	Power splitting, different voltage zones
L4	Bottom (signal layer)	Low-speed signals, interfaces, test points

Advantages: L1 to L2 are tightly coupled, signal loop impedance is low, good EMI; L4 to L3 also has a complete reference plane. Disadvantages: L3 and L2 dielectric is relatively thick. If power splitting is not good, signals crossing splits will have discontinuous reference planes.

Scheme B: Signal-Power-Ground-Signal

Layer	Name	Purpose
L1	Top (signal layer)	High-speed signals
L2	PWR (power plane)	Power splitting
L3	GND (ground plane)	Complete reference plane
L4	Bottom (signal layer)	Low-speed signals

Advantages: Power and ground are adjacent, inter-layer capacitance helps with decoupling. Disadvantages: L1 coupling to the nearest reference plane (L2 power layer) is not as good as Scheme A, because the power layer often has splits.

Recommendation: For most projects, Scheme A is safer. Prioritize high-speed signals on L1, keep reference plane L2 complete without splits.

6. Impedance Control: Lifeline of High-Speed Signals

When frequency exceeds 50MHz, traces become transmission lines. Impedance mismatch brings reflection, overshoot, ringing.

Microstrip Impedance Approximation Formula

L1 and L4 traces are microstrip structures:

Z0 ≈ (87 / √(Er + 1.41)) × ln(5.98 × H / (0.8 × W + T))

Er: Dielectric constant (FR-4 about 4.2~4.5)
H: Distance from trace to reference plane
W: Trace width
T: Copper thickness (1oz ≈ 35μm)

Practical Experience Values for 1.6mm Board Thickness / 1oz Copper / FR-4

Target Impedance	Trace Width	Application
50Ω single-ended	0.2~0.25mm	UART, SPI, general digital signals
90Ω differential	0.15mm / spacing 0.15mm	USB D+/D-
100Ω differential	0.15mm / spacing 0.12mm	Ethernet, HDMI
120Ω differential	0.12mm / spacing 0.1mm	CAN bus

KiCad has a built-in KiCad Impedance Calculator plugin, or use the open-source Saturn PCB Toolkit:

flatpak install flathub org.kaimet.saturn-pcb-toolkit

Three Steps for Impedance Matching

Confirm dielectric thickness and Er in the stackup manager, use the calculator to get theoretical trace width.
Communicate with the board manufacturer about actual process capabilities, fine-tune trace width and spacing according to their stackup parameters.
Keep trace width consistent at connector and via transitions to avoid impedance discontinuity.

7. Crosstalk Suppression and Power Integrity

Three Countermeasures for Crosstalk

3W rule: Adjacent signal trace center-to-center distance ≥ 3 × trace width, can reduce capacitive coupling by about 70%.
Ground guard: Add ground traces between sensitive signals (clock, RF), place ground vias every λ/10 to connect ground, avoid the ground trace itself becoming an antenna.
Orthogonal routing between layers: L1 horizontal routing, L4 vertical routing, crosstalk is about 50% lower than same-direction routing.

Power Splitting and Decoupling

Isolate different voltage zones (3.3V / 5V / 1.8V) with slots, slot width ≥ 0.5mm.
Signals crossing splits must have a “via bridge” or continuous reference plane path, otherwise the return path is cut off.
Decoupling capacitor layout requirements: Chip power pin → very short trace (< 2mm) → 0.1μF 0402/0603 capacitor → adjacent via → ground plane.
At least one 0.1μF per power pin; high-speed chips like FPGA, DDR need additional 1~10μF.

8. Four-Layer Board KiCad Practical Workflow

1. Set Up Stackup

Board Editor → Setup → Board Stackup Manager
Layer 1: F.Cu   (Top)   - Signal
Layer 2: In1.Cu (GND)   - Plane
Layer 3: In2.Cu (PWR)   - Plane
Layer 4: B.Cu   (Bottom)- Signal
Core: 0.2mm (L1-L2)
Prepreg: 0.2mm (L2-L3)
Core: 0.96mm (L3-L4)

2. Place Power Plane

Press B to draw power areas on the In2.Cu layer, right-click Properties to set Net to +3V3.

3. Routing Priority

First route all high-speed signals (clock, DDR, USB, Ethernet), maintain impedance continuity.
Then route power and high-current paths, choose trace width according to current.
Then route normal low-speed signals (UART, SPI, I2C).
Finally, copper pour, add ground vias, handle silkscreen and outline.

4. DRC Check

KiCad → Tools → Design Rules Checker (F11)

Key checks: minimum trace width/spacing (≥ 0.15mm), differential pair length difference (USB ≤ 5mil, Ethernet ≤ 10mil), power/ground shorts.

5. Output Gerber

KiCad → File → Fabrication Outputs → Gerbers
- Check Use Protel Extensions
- Check Exclude Editor Visibles
- Preview layer by layer after generation

Use GerbView or PCBWay Viewer to confirm layer by layer to avoid surprises.

9. Common Troubleshooting Quick Reference

Severe Signal Overshoot

Use an oscilloscope to measure rise time, confirm overshoot amplitude and frequency.
Check if trace impedance is continuous, if there’s widening/narrowing at connectors.
Confirm reference plane is complete, no crossing splits.
Add series termination resistors if necessary (usually 22~33Ω).

High Power Noise, Ripple Exceeds ±5%

Check if decoupling capacitors are close to chip pins.
Confirm power traces are wide enough (≥ 0.5mm).
Check if power plane has return paths crossing splits.
Use oscilloscope to observe ripple under different loads, locate noise source.

EMI Test Failure

Use spectrum analyzer to locate exceeding frequency points, correlate to specific clock or signal.
Check if that signal’s reference plane is continuous.
Add ground vias, shield traces, or add ferrite beads.
Check if connector shells are properly grounded.
Add spread spectrum (SSC) to clock lines if necessary.

Poor Differential Signal Quality (USB enumeration fails, Ethernet packet loss)

Check if differential pair impedance matches (90Ω / 100Ω).
Check if length difference is within allowed range.
Confirm traces don’t cross reference plane splits.
Check if connector pads and trace impedance are continuous.

10. Final Checklist Before Prototyping

□ Stackup scheme confirmed (recommend Signal-Ground-Power-Signal)
□ Impedance calculation completed (50Ω single-ended, 90/100Ω differential)
□ Critical signal routing completed (clock, differential pairs)
□ 3W rule check passed
□ Power plane splitting is reasonable
□ Decoupling capacitor layout is correct
□ DRC zero errors
□ Differential pair length matching checked
□ Gerber preview confirmed correct
□ Drill files (Excellon) generated

JLCPCB prototyping tips: minimum trace width/spacing 0.15mm (6mil), minimum drill 0.3mm, green solder mask is cheapest, small boards can be panelized to reduce unit price; after uploading Gerber, be sure to preview with DFM tool.

Summary

PCB design is not “drawing lines”, it’s designing the propagation path of electromagnetic fields. Break down the process clearly, have checkpoints at every step, it’s much more efficient than drawing everything at once and then going back to fix. Three core principles:

Reference plane determines everything — four-layer board stackup scheme, impedance control, return paths, all revolve around “complete reference plane”.
Power and signals are equally important — decoupling, splitting, trace width, if any link fails, the entire board’s signals will be affected.
Process before technique — schematic → footprint → layout → routing → DRC → Gerber, confirm step by step in order, don’t skip steps, don’t go back.

Even if you’re just drawing a simple ESP32 breakout board, after going through this process, your perspective on any hardware product will be different.

Hope this blog post is helpful to you!