Jun 29, 2026 Hardware and Design

FT601 Chip Getting Started Guide: USB 3.0 High-Speed FIFO Bridge Detailed Explanation

FT601 is a high-performance USB 3.0 to FIFO bridge chip from Future Technology Devices International (FTDI), designed specifically for applications requiring high-speed data transmission. This article will comprehensively introduce FT601’s technical features, working principles, development process, and typical application cases.

Chip Overview

FT601 is a USB 3.0 SuperSpeed (5Gbps) to parallel FIFO interface bridge chip, belonging to FTDI’s SuperSpeed series along with the FT600 series. Main technical specifications are as follows:

Interface Type: USB 3.0 SuperSpeed (5Gbps) / USB 2.0 High Speed (480Mbps) / USB 2.0 Full Speed (12Mbps)
FIFO Bus Width: 32-bit wide parallel interface (FT600 is 16-bit)
Package Type: 76-pin QFN package
Data Throughput: Up to 400MB/s (theoretical peak)
Operating Modes: Supports both 245 mode and FIFO mode parallel slave protocols

FT600 vs FT601 Key Differences

Feature	FT600	FT601
FIFO Bus Width	16-bit	32-bit
Package Pin Count	56 pins	76 pins
Data Throughput	~200MB/s	~400MB/s
Application Scenarios	Medium bandwidth requirements	High bandwidth requirements

💡 Simply put: FT601 is the performance upgrade of FT600, achieving double the data throughput capability through doubled bus width, suitable for applications with extremely high bandwidth requirements such as FPGA, high-speed ADC/DAC, video capture, etc.

Working Principle

FT601’s internal architecture includes USB 3.0 PHY, USB controller, FIFO buffer, and parallel interface controller. Its core workflow is as follows:

USB Side: Receives USB 3.0 data packets from the host, unpacks and stores them in the internal FIFO buffer
FIFO Management: Uses dual-buffer mechanism, supports automatic flow control and interrupt notification
Parallel Side: Communicates with external devices (such as FPGA) through a 32-bit wide parallel bus (address/data multiplexed or separate)
Timing Control: Supports programmable read/write timing, adapting to different host device timing requirements

Typical Application Scenarios

FPGA Data Transmission: As a high-speed data channel between FPGA and PC, replacing traditional PCIe or Ethernet solutions
Test and Measurement Equipment: Data acquisition interface for high-speed oscilloscopes, logic analyzers
Industrial Automation: Real-time image data transmission in machine vision systems
Software Defined Radio (SDR): High-speed transmission of baseband signals
Medical Imaging Equipment: Raw data transmission for ultrasound, MRI and other equipment

Development Guide

Hardware Design Key Points

Power Design: FT601 requires both 3.3V and 1.2V power supplies, pay attention to power ripple requirements
Clock Source: 24MHz crystal oscillator recommended, accuracy requirement ±100ppm
Impedance Matching: USB 3.0 differential lines need strict control of 50Ω single-ended/100Ω differential impedance
FIFO Interface: 32-bit data bus recommended to use LVCMOS 3.3V level

Software Development Environment

Drivers: FTDI provides Windows/Linux/macOS full-platform drivers
Development Libraries: D2XX Direct Drivers (low-level control) and Virtual COM Port (VCP) drivers
Development Tools: FTDI’s FT60x Configuration Utility for chip configuration

Complete Development Process

Hardware Design: Complete FT601 schematic and PCB design
Firmware Development: Write FPGA logic or MCU firmware to handle FIFO protocol
Driver Integration: Integrate FTDI driver and application on the host side
Performance Tuning: Optimize FIFO depth, interrupt thresholds and bulk transfer sizes
Certification Testing: Conduct USB-IF compatibility testing and EMC testing

Frequently Asked Questions

Q: Does FT601 support hot-plugging?

A: Yes, FT601 fully supports USB standard hot-plugging functionality, no additional circuits required.

Q: How to optimize data transmission performance?

A: Key parameters include: increase FIFO buffer depth, adjust bulk transfer size (recommend 512KB), enable multi-threaded data processing, optimize host-side DMA configuration.

Q: How to connect FT601 with Xilinx Zynq’s PS-PL interface?

A: It’s recommended to use AXI-Stream interface with FT601’s FIFO mode, achieving zero-copy data transmission through AXI DMA controller.

Summary

As a mature USB 3.0 high-speed bridge chip, FT601 has become the preferred solution for high-speed data transmission applications with its 400MB/s theoretical bandwidth, stable driver support and rich development resources. Compared to complex interfaces like PCIe, FT601 provides a simpler, lower-cost high-speed data channel solution.

For engineers who need to establish high-speed data links between FPGA, ASIC or MCU and PC, FT601 is undoubtedly an excellent chip worthy of in-depth research and application.

📚 Reference Materials:

FT600Q-FT601Q IC Datasheet

SuperSpeed Series Factsheet

FT60x Timing Closure and Tips

Pin Description and Typical Application Circuit

FT601’s 76-pin QFN package contains the following key signal groups:

Power Pins

Pin Name	Voltage	Description
VCC	3.3V	Main power input
VCCIO	1.2V	FIFO interface IO power
GND	-	Ground

FIFO Interface Signals (Parallel Side)

Signal Name	Direction	Description
DATA[31:0]	Bidirectional	32-bit data bus
BE[3:0]	Bidirectional	Byte enable signals (4-byte aligned)
RXF#	Output	Receive FIFO full flag (active low)
TXE#	Output	Transmit FIFO empty flag (active low)
RD#	Input	Read enable signal (active low)
WR#	Input	Write enable signal (active low)
OE#	Input	Output enable signal (active low)

USB Interface Signals

Signal Name	Description
USB_DP/USB_DM	USB 2.0 D+/D-
USB3_SSRX+/SSRX-	USB 3.0 SuperSpeed receive differential pair
USB3_SSTX+/SSTX-	USB 3.0 SuperSpeed transmit differential pair

Typical Application Circuit

Typical FT601 application circuits include:

24MHz crystal oscillator circuit: Connect to OSC_IN and OSC_OUT pins, matching capacitors recommend 22pF
USB 3.0 interface: Connect to PC through USB Type-C or Type-A connector, pay attention to AC coupling capacitors
FIFO side connected to FPGA: 32-bit data lines directly connected to FPGA’s GPIO or dedicated FIFO interface
Power filtering: Each VCC pin equipped with 100nF decoupling capacitor, VCCIO equipped with 10uF storage capacitor

Comparison with Alternative Solutions

In high-speed USB bridging solutions, FT601 has several common alternatives:

Feature	FT601	FT2232H	CY7C68013A (FX2LP)
USB Version	USB 3.0 SuperSpeed	USB 2.0 High Speed	USB 2.0 High Speed
Theoretical Bandwidth	400MB/s	About 12MB/s	About 40MB/s
Data Bus Width	32-bit	8/16-bit	8/16-bit
Package	76-pin QFN	48-pin QFP	100-pin TQFP
Price (Reference)	Medium-high	Low	Medium
Driver Support	FTDI official full-platform	FTDI official full-platform	Cypress official (discontinued)
Suitable Scenarios	High bandwidth data acquisition	Low-speed control/debugging	Medium bandwidth video capture

Selection Recommendations:

Need bandwidth over 50MB/s → FT601
Simple low-speed control interface (such as UART/SPI/I2C bridging) → FT2232H
Limited budget and low bandwidth requirements → CY7C68013A (note not recommended for new designs)

Development Process Detailed Explanation

1. Driver Installation

FTDI officially provides D3XX (D3XX is FT601’s dedicated Direct Driver) driver:

Windows: Download FT60x D3XX Driver installation package from FTDI official website, supports Win10/11
Linux: Need to install udev rules file, grant FTDI device permissions to current user

Linux installation steps:

# Download Linux driver
wget https://ftdichip.com/wp-content/uploads/FTDI-Linux-D3XX-x64.tar.gz
tar -xzf FTDI-Linux-D3XX-x64.tar.gz

# Install udev rules
sudo cp ftdi.rules /etc/udev/rules.d/
sudo udevadm control --reload-rules

# Install dynamic library
sudo cp libftd3xx.so /usr/lib/

2. D3XX Library Basic Usage

D3XX is FT601’s dedicated low-level API, compared to VCP (virtual serial port) mode, performance is several times higher.

3. Basic Read/Write Code Example

Here’s a basic read/write example using C language and D3XX library:

#include "ftd3xx.h"
#include <stdio.h>
#include <string.h>

int main() {
    FT_HANDLE ftHandle = NULL;
    FT_STATUS ftStatus;
    FT_DEVICE_LIST_INFO_NODE devInfo;
    DWORD numDevices = 0;

    // Enumerate devices
    ftStatus = FT_CreateDeviceInfoList(&numDevices);
    if (ftStatus != FT_OK || numDevices == 0) {
        printf("No FT601 device found\n");
        return -1;
    }
    printf("Found %lu FT601 devices\n", numDevices);

    // Open first device
    ftStatus = FT_Create(0, FT_OPEN_BY_SERIAL_NUMBER, &ftHandle);
    if (ftStatus != FT_OK) {
        printf("Failed to open device\n");
        return -1;
    }

    // Write data to FIFO (send to external device)
    unsigned char writeBuffer[1024];
    memset(writeBuffer, 0xAA, sizeof(writeBuffer));
    DWORD bytesWritten = 0;

    ftStatus = FT_WritePipe(ftHandle, 0x02, writeBuffer, sizeof(writeBuffer), &bytesWritten, NULL);
    printf("Wrote %lu bytes, status: %d\n", bytesWritten, ftStatus);

    // Read data from FIFO (from external device)
    unsigned char readBuffer[1024];
    DWORD bytesRead = 0;

    ftStatus = FT_ReadPipe(ftHandle, 0x81, readBuffer, sizeof(readBuffer), &bytesRead, NULL);
    printf("Read %lu bytes, status: %d\n", bytesRead, ftStatus);

    // Close device
    FT_Close(ftHandle);
    return 0;
}

Compilation command:

gcc -o ft601_test ft601_test.c -lftd3xx

Bandwidth Test Actual Results

In actual testing, we used FT601 with Xilinx Artix-7 FPGA for bandwidth testing:

Test Scenario	Actual Bandwidth	Notes
Pure read (FPGA→PC)	About 320MB/s	Close to 80% of theoretical peak
Pure write (PC→FPGA)	About 280MB/s	Affected by FIFO depth
Bidirectional simultaneous read/write	Read 260MB/s + Write 240MB/s	Total bandwidth limited by USB 3.0
Small packet transfer (64 bytes)	About 15MB/s	Packet overhead significant

Optimization Recommendations:

Use at least 16KB transfer block size, avoid frequent small packet transfers
FPGA-side FIFO depth recommended 4KB or above, reduce flow control waiting
Host side use asynchronous IO or multi-threaded processing, avoid CPU becoming bottleneck
Ensure USB cable quality meets standards, poor quality cables will cause speed drop to USB 2.0 mode